1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same. More particularly, the present invention relates to a single transistor memory device having insulating regions associated with the source and drain regions, and a method of fabricating the same.
2. Description of the Related Art
A conventional dynamic random access memory (DRAM) cell, which is a type of volatile memory, typically incorporates a capacitor, a transistor and interconnection units. In response to demands for electronic devices to be increasingly lightweight, small and thin, DRAM cells have become more highly integrated. That is, as many DRAM cells as possible are formed within a restricted space However, the technology of highly integrating DRAM cells faces several limitations.
For example, a typical DRAM cell capacitor includes upper and lower electrodes, and a capacitor dielectric layer. The upper and lower electrodes share an overlapping region, and the capacitor dielectric layer is positioned between the upper and lower electrodes. The capacitance of the capacitor is directly proportional to the size of the overlapping region, and inversely proportional to a thickness of the overlapping region. A minimum area for forming a capacitor is therefore required.
A single transistor floating-body DRAM cell has been developed, which includes a floating body region for storing data. Because there is no capacitor, the single transistor floating-body DRAM cell may be more highly integrated than a common DRAM cell having a capacitor.
A capacitor-less, single transistor DRAM cell is described, for example, in an article entitled “Scaled IT-bulk Devices Built with CMOS 90 nm Technology for Low-cost eDRAM Applications” by R. RANICA (IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 38-39 (2005)). FIG. 1 herein is a cross-sectional view of a single transistor DRAM cell like that disclosed in the RANICA article.
Referring to FIG. 1, a semiconductor substrate 1 includes a deep n-well 3 and a pocket p-well 5 located in the deep n-well 3. An isolation layer 7 is located within a predetermined region of the pocket p-well 5, defining an active layer 5a of the pocket p-well 5. The isolation layer 7 is in contact with the deep n-well 3 through the pocket p-well 5. As a result, the active region 5a functions as an electrically floated bulk region, which is surrounded by the isolation layer 7 and the deep n-well 3.
Source and drain regions 16s and 16d are respectively located in both ends of the bulk region 5a, and a gate pattern 10 is located on the bulk region 5a between the source and drain regions 16s and 16d. The gate pattern 10 includes a gate insulating layer 8 and a gate electrode 9, which are sequentially stacked. A spacer 13 may be located on a sidewall of the gate pattern 10. The source region 16s may include a heavily-doped source region 15s spaced apart from the gate pattern 10, and a lightly-doped source region 11s extending from the heavily-doped source region 15s. Likewise, the drain region 16d may include a heavily-doped drain region 15d spaced apart from the gate pattern 10, and a lightly-doped drain region 11d extending from the heavily-doped drain region 15d. The lightly-doped source and drain regions 11s and 11d may be located beneath the spacer 13.
According to RANICA, the source and drain regions 16s and 16d are shallower in thickness than the active region 5a, i.e., the bulk region, as illustrated in FIG. 1. Thus, the bulk region 5a may also extend under the source and drain regions 16s and 16d. As a result, during a program operation, the number of holes stored in the bulk region 5a is maximized. However, the holes stored in the bulk region 5a may be recombined with electrons in the source and drain regions 16s and 16d after program operation, and erased in a short period of time. In other words, the single transistor DRAM cell illustrated in FIG. 1 has poor data retention characteristics.
Furthermore, when the source and drain regions 16s and 16d have large junction areas, junction capacitances Cs and Cd of the source and drain regions 16s and 16d also increase. Thus, a loading capacitance of a bit line electrically connected to the drain region 16d increases, which may lead to a decrease in a data sensing margin and operating speed of the single transistor DRAM cell.
Another example of a single transistor floating-body DRAM device is disclosed in U.S. Patent Application Publication No. 2006/0049444, entitled “Semiconductor Device and Method of Fabricating the Same” by SHINO. According to SHINO, a floating body having a single crystal structure is located on a semiconductor substrate. The floating body has an expanded structure capable of storing excess holes, although the excess holes may be easily erased through source and drain regions.